The official specification of ATM motherboard was released by Intel, wherein the power supply can be manipulated by the computer system itself instead of the mechanical switch. Afterward, an ACPI (advanced configuration and power interface) specification is developed by Intel, Microsoft and Toshiba to implement power management functions in the operation system. The ACPI specification switches a computer between five states according to system's current activity. The states represent the further reduction in power use and are as follows: S1, S2: power on suspend, S3: suspend to RAM, S4: suspend to disk, and S5: Soft-off. In the suspend-to-RAM state, the components on the motherboard, including the clock generator and CPU, are stopped except the real-time clock.
The conventional control circuit for the suspend—to RAM mode is shown in FIG. 1, which comprises a RAM controller 10a (generally arranged in the North bridge chip) connected to a RAM 20a (composed of RAM modules m1–m3). The RAM controller 10a has control pins J1–J6 connected to the first enable pin CKE0 and the second enable pin CKE1 of the RAM modules m1–m3, respectively. Therefore, the RAM controller 10a can trigger the RAM modules m1–m3 into the suspend to RAM mode through the control pins J1–J6, wherein the computer system stops all executing programs and stores operational parameters into the RAM modules m1–m3. At this time, the power consumption is greatly reduced.
However, the nowaday computer system generally requires a large amount of RAM modules (for example, in server application), for example, 8 RAM modules. In this concern, the RAM controller 10a needs more reserved control pins for connecting to the first enable pin CKE0 and the second enable pin CKE1 of the RAM modules. Conventionally, the control pins are increased at the expense of the memory debug pins DQM0–DQM7 and ECCD0–ECCD7 or other pins. Alternatively, the control pins are increased by increasing the pin count of the RAM controller 10a. In the former case, the dedicated function provided by the memory debug pins DQM0–DQM7 and ECCD0–ECCD7 are sacrificed. In the later case, the complexity of the North bridge chip design and cost are increased.